1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a layout method thereof and relates to, in particular, a semiconductor integrated circuit wherein pad block macros are arranged on peripheral portions of a chip and hardware macros and standard cells are arranged inside the chip using an automatic layout and wiring program, and to a layout method thereof.
2. Description of the Related Art
An automatic layout method using a standard cell having a standardized height has been mainly used for the layout of a semiconductor integrated circuit device referred to as an ASIC in recent years. Due to packaging standards, measures against, for example, latch-up destruction, electrostatic destruction and noise, the layout of input terminals, output terminals and input/output terminals and peripheral elements relating to them is given more limitations than the layout of internal chips. For that reason, there are many cases where input and output terminals are formed into hardware macros as pad blocks.
FIG. 1 is a plan view showing an example of a semiconductor integrated circuit device arranged using the above-stated pad blocks. Chip regions are roughly divided into two parts; a pad region 401 in which pad blocks are arranged and an internal region 402 in which other circuits are arranged. In the internal region 402, there are arranged hardware macros 403 such as a ROM, a RAM and an A/D converter, and a standard cell 404. Input and output wirings (not shown) are arranged between the layout of the internal region 402 and pad blocks 405, respectively.
The interior of the pad block 405 is arranged as shown in, for example, FIG. 2. A reference numeral 501 denotes a pad for wire bonding, a reference numeral 502 denotes an output buffer/protecting circuit having an electrostatic destruction protecting function, a reference numeral 503 denotes a wiring for connecting the pad 501 to the output buffer/protecting circuit 502. A reference numeral 504 denotes a guard ring for preventing latch-up, a reference numeral 505 denotes an internal circuit for driving the output buffer/protecting circuit 502 and a reference numeral 506 denotes a wiring for connecting the output buffer circuit to the internal circuit 505.
FIG. 3 shows another example of the layout of a pad block. This exemplifies a case where an internal circuit is separated from the pad block. A reference numeral 601 denotes a bonding pad, a reference numeral 602 denotes an output buffer/protecting circuit, reference numeral 603 denotes a wiring for connecting the pad 601 to the output buffer, a reference numeral 604 denotes a guard ring for preventing latch-up, and a reference numeral 605 denotes an arrangement forbidden region in which the layout of elements and other blocks are forbidden.
Now, the reason for providing the arrangement forbidden region 605 in hard macros shown in FIG. 3 will be described. The internal circuit needs to be arranged to have predetermined distances from the guard ring and the buffer circuit provided within the pad block for preventing latch-up. In the example of FIG. 2, part of the internal circuit is incorporated into the pad block and a certain distance is maintained between the output buffer circuit and the internal circuit. Due to this , there is no need to consider this distance when arranging integrated circuit chips. In the example of FIG. 3, on the other hand, where the internal circuit is separated from the pad block, it is required to maintain distances for preventing latch-up no matter which block is adjacent to the pad block. It is, therefore, necessary to provide a forbidden region in advance so as not to arrange the internal circuit block.
The integrated circuit chips are arranged by procedures as shown in the flow chart of FIG. 4, after preparing necessary pad blocks, hardware macros and a standard cell. First, in step S1, pad optimum position coordinates are calculated from an anticipated chip size and a package to be used. Pad blocks are then arranged on the optimum position coordinates in step S2. Hardware macros are arranged in the internal region in step S3. After special wirings such as a power supply are wired in step S4, an automatic arrangement wiring is then executed on the overall chips in step S5. As wirings, pre-defined wiring layers, such as the first wiring layer in X direction and the second wiring layer in Y direction, are used.
FIG. 5 is a layout diagram showing a wiring state in which the internal region 802 is connected to pad blocks 801 shown in FIG. 2. Also, as shown in the figure, each of the pad blocks 801 comprises a guard ring 803. As shown therein, ports from which wirings are taken out from the internal region 802 and those from which wirings are incorporated into the internal region 802 are not necessarily provided adjacent to the corresponding pad blocks. In case of employing inexpensive chips, in particular, wiring layers are limited to two layers or the like to hold down production costs. Due to this, wirings are allowed to pass through only limited portions of the internal region and ports for taking out wirings from pad blocs and those for incorporating them into the pad blocks are sometimes provided rather distant away from the corresponding pad blocks. As a result, as shown in FIG. 5, it is necessary to provide a region for detouring wirings 805 between the internal region 802 and the pad blocks 801. In addition, the wirings 805 are connected via through holes 804. In circumstances where integrated circuits are becoming smaller in size and so is the inner layout, an area used for arranging wirings around pads has a great influence on the chip size. Considering this, it is of importance to efficiently arrange peripheral portions of pad blocks and the detoured circuit wiring region, shown in FIG. 5, greatly causes a reduction in chip area.
FIG. 6 shows another example of a layout when the pad blocks shown in FIG. 3 are used. Each of the pad blocks 901 is provided with an arrangement forbidden region 904 with a guard ring 903. An internal circuit 905 is arranged inside the pad block 901. The internal circuit 905 is connected to the circuit of the internal region 902 via a wiring and a through hole.
The pad block of such a type as shown in FIG. 3 is arranged to be separated from the internal circuit. Due to this, to arrange integrated circuit chips, the pad blocks and internal circuit blocks should be arranged in pairs. As shown in FIG. 6, therefore, the layout forbidden region 904 between an internal circuit block and the guard ring 903 of a pad block can be used for wiring. In this method, however, not only a wiring region needs to provided be between the internal circuit 905 and the internal region 902 and but also the number of steps increases since a step for arranging internal circuit blocks needs to be added to a step for arranged pad blocks.